Manan Dua

Introduction

In this project, two voltage-controlled switches were designed, built, and tested using CD4007 MOSFET arrays. Each switch’s performance was evaluated against the ideal-switch model by examining four non-idealities: on-state resistance (Ron), off-state leakage (Roff), limited voltage range, and bidirectional capability. Measurements were compared to LTSpice simulations to understand practical deviations.

Switch Type 1: Single transmission gate formed by an NMOS and PMOS in parallel, controlled by Vcontrol and its inverse. Switch Type 2: Two transmission gates arranged to select between two outputs (VA or VB), behaving like a 2:1 multiplexer.

Ideal vs. Non-Ideal Switches

Ideal Switch Properties

An ideal switch has:

  • Zero on-state resistance (Ron = 0), producing no voltage drop or power loss.
  • Infinite off-state resistance (Roff → ∞), ensuring zero leakage current when open.
  • Ability to handle any voltage difference without breakdown.
  • Constant Ron, independent of applied voltage.

Non-Idealities

Real switches exhibit:

  • Non-zero Ron: Measurable voltage drop and power dissipation in ON state.
  • Finite Roff: Leakage current flows when switch is OFF.
  • Limited Voltage Range: Switch only operates within a certain Vin range.
  • Directional Dependence: Ron may differ depending on current direction.

Test Plan

Each switch was tested under four conditions to quantify non-idealities. In all tests, a 10 kΩ pull-down resistor was used at the output terminal(s) to ensure a measurable voltage drop.

  1. On-State Resistance (Ron): Apply V1=5 V, Vcontrol=0 V, measure Vout, calculate Ron via voltage divider.
  2. Off-State Leakage (Ileak): Apply V1=5 V, Vcontrol=5 V, measure Vout, compute leakage current and Roff.
  3. Operating Voltage Range: Apply a 5 Vpp sinusoid at 10 Hz to V1, Vcontrol=0 V, observe Vout vs. Vin to identify threshold anomalies.
  4. Bidirectional Operation: Swap input to previously output node with Vcontrol=0 V, measure Vother, compute reverse Ron.

Switch Type 1

Circuit Description

Switch 1 is a single transmission gate implemented on a CD4007. An NMOS and PMOS are arranged in parallel, with gates driven by Vcontrol and its inverted signal (generated via two additional MOSFETs). This ensures conduction for any input between 0 V and 5 V.

Switch 1 LTSpice Schematic (Figure 5)
Switch 1 Physical Build (Figure 6)

Physical Build

Assembled on a solderless breadboard using a CD4007 IC, two 1N4148 diodes (for control inversion), and a 10 kΩ pull-down resistor at Vout (V2).

On-State Resistance (Ron)

Test Conditions: Vsupply=5 V, V1=5 V, Vcontrol=0 V, 10 kΩ pull-down at V2. Measured V2≈4.75 V, so: 

Ron = [V1 × 10 kΩ / V2] – 10 kΩ = [5 V × 10 kΩ / 4.75 V] – 10 kΩ ≈ 526 Ω
V<sub>2</sub> Measurement for R<sub>on</sub> (Figure 7)

Off-State Leakage (Ileak)

Test Conditions: Vsupply=5 V, V1=5 V, Vcontrol=5 V, 10 kΩ pull-down at V2. Measured V2≈19.2 mV ⇒ Ileak=19.2 mV/10 kΩ≈1.92 µA. ⇒ Roff≈[5 V × 10 kΩ / 0.0192 V] – 10 kΩ ≈ 2.59 MΩ.

V<sub>2</sub> Measurement for Leakage (Figure 8)

Operating Voltage Range

Test Conditions: Vsupply=5 V, V1=5 Vpp sinusoid at 10 Hz (±2.5 V), offset 2.5 V, Vcontrol=0 V, 10 kΩ pull-down at V2. Measured V2 follows V1 for most of 0–5 V range, but deviation at ~2.4 V due to MOSFET threshold mismatches.

V<sub>2</sub> vs. V<sub>1</sub> (Figure 9)
Reverse R<sub>on</sub> Measurement (Figure 10)

Bidirectional Operation

Test Conditions: Vsupply=5 V, V2=5 V, Vcontrol=0 V, 10 kΩ pull-down at V1. Measured V1≈4.76 V ⇒ Ron,reverse≈[5 V × 10 kΩ / 4.76 V] – 10 kΩ ≈ 504 Ω. Similar to forward Ron, confirming bidirectional conduction.

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Theoretical Explanation

Switch 1 is a CMOS transmission gate: NMOS and PMOS in parallel ensure that for any Vin (0–5 V), one device is in conduction. Vcontrol drives both gates; an inverter (two additional MOSFETs) provides the complementary gate drive. In ON state, both devices conduct; in OFF state, both are cut off.

Transmission Gate Operation (Figure 11)

Design Trade-offs

  • Requires 4 MOSFETs on a CD4007, leaving 2 unused—inefficient IC utilization.
  • Measured Ron (~500 Ω) far exceeds ideal (2–3 Ω) due to 10 kΩ load and device parameters.
  • Differing NMOS/PMOS thresholds cause voltage-range anomaly at ~2.4 V.

Switch Type 2

Circuit Description

Switch 2 extends Switch 1 by adding a second transmission gate (TG2) controlled by the inverted Vcontrol. TG1 connects V1 to VA when Vcontrol=0 V; TG2 connects V1 to VB when Vcontrol=5 V. Thus, only one of VA or VB is connected at a time.

Switch 2 LTSpice Schematic (Figure 12)
Switch 2 Physical Build (Figure 13)

Physical Build

Built on a breadboard using two CD4007 ICs (one per transmission gate), plus two inverters for complementary control. 10 kΩ pull-down resistors on VA and VB.

On-State Resistance (Ron)

Test Conditions (VA): Vcontrol=0 V, Vsupply=5 V, V1=5 V, pull-downs on VA/VB=10 kΩ. Measured VA≈4.76 V ⇒ Ron,A≈504 Ω.

Test Conditions (VB): Vcontrol=5 V, same setup. Measured VB≈4.76 V ⇒ Ron,B≈504 Ω.

V<sub>A</sub> and V<sub>B</sub> Measurement for R<sub>on</sub> (Figure 14)
Leakage Measurement (Figure 15)

Off-State Leakage (Ileak)

Test Conditions (VB off): Vcontrol=0 V, Vsupply=5 V, V1=5 V, pull-downs=10 kΩ. Measured VB≈45.0 mV ⇒ Ileak,B≈4.5 µA ⇒ Roff,B≈1.10 MΩ.

Test Conditions (VA off): Vcontrol=5 V, same setup. Measured VA≈43.3 mV ⇒ Ileak,A≈4.33 µA ⇒ Roff,A≈1.14 MΩ.

Operating Voltage Range

Test Conditions (VA): V1=5 Vpp sinusoid at 10 Hz, offset 2.5 V, Vcontrol=0 V, pull-down on VA=10 kΩ. VA follows V1 for 0–5 V, minor deviation at ~2.4 V. Test Conditions (VB): Vcontrol=5 V, pull-down on VB, similar results.

V<sub>A</sub> and V<sub>B</sub> vs. V<sub>1</sub> (Figure 16)
Bidirectional Test (Figure 17)

Bidirectional Operation

Test Conditions (VA→V1): Vcontrol=0 V, VA=5 V, pull-down on V1=10 kΩ. Measured V1≈4.76 V ⇒ Ron,reverse≈504 Ω. Test Conditions (VB→V1): Vcontrol=5 V, VB=5 V, pull-down on V1. Measured V1≈4.76 V ⇒ Ron,reverse≈504 Ω. Confirms bidirectional conduction.

Theoretical Explanation

Switch 2 uses two transmission gates controlled by Vcontrol and its inverse to select between VA and VB. When Vcontrol=0 V, TG1 connects V1 to VA, TG2 is OFF. When Vcontrol=5 V, TG2 connects V1 to VB, TG1 is OFF. Each transmission gate behaves like Switch 1.

Switch 2 Transmission Gates (Figure 18)

Design Trade-offs

  • Requires two CD4007 ICs to implement both transmission gates—higher cost (~\$1.88) and unused MOSFETs.
  • Measured Ron (~500 Ω) and deviations at 2.4 V similar to Switch 1.
  • Functionally resembles a multiplexer; reverse current only flows to V1, not between VA and VB.

References

  1. “CD4007UB Types,” Texas Instruments, https://www.ti.com/lit/ds/symlink/cd4007ub-mil.pdf, accessed Feb. 27, 2025.
  2. W. Storr, “Transmission gate as a CMOS bilateral switch,” Basic Electronics Tutorials, https://www.electronics-tutorials.ws/combination/transmission-gate.html, accessed Feb. 26, 2025.
  3. A. S. Sedra, K. C. Smith, T. C. Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed. New York, NY: Oxford University Press, 2019.