Manan Dua

Summary

Logic gates form the basis of digital circuits, and MOSFETs act as voltage-controlled switches. NMOS transistors conduct when their gate is high, while PMOS conduct when their gate is low [1]. CMOS logic uses complementary NMOS and PMOS networks—Pull-Down Network (PDN) of NMOS and Pull-Up Network (PUN) of PMOS—to build efficient, low-power gates. This project implements and tests a CMOS XOR gate using CD4007B arrays.

Design

The XOR function’s Boolean expression is simplified via De Morgan’s theorem. Truth table:

ABF
000
011
101
110

F = A ⊕ B = A̅B + A B̅ ⇒ (A̅B)̅ · (A B̅)̅ ⇒ (A + B̅) · (A̅ + B)

PDN: A·B̅ in series with A̅·B in parallel. PUN: series/parallel reversed using PMOS transistors. Inversions of A and B require two MOSFETs each. Total: 12 MOSFETs.

Ideal vs. Real Switch Comparison (Figure 2)

Ideal Sizing

To minimize delay, PUN and PDN should be symmetric. Propagation delays: 

τPHL = 0.69 RN CL = 4.14 CL
τPLH = 0.69 RP CL = 4.14 CL

Electron mobility is 2.5× hole mobility; thus ideal width ratios: (W/L)P:(W/L)N = 2.5:1. For worst-case (two MOSFETs in series), size should double: (W/L)P=10:1, (W/L)N=4:1. CD4007B has fixed sizes—ideal sizing not implementable. Propagation delay will be 2× τref.

CMOS XOR Gate Implementation

The XOR gate uses two transmission gates (Switch 1 for A·B̅ and Switch 1 mirrored for A̅·B) arranged in PDN and PUN. Inputs A and B feed inverters (two MOSFETs each) for control. Total MOSFET count: 12.

Physical CMOS XOR Gate (Figure 3)

Physical Build

Constructed on breadboard using one CD4007B IC. All 6 NMOS and 6 PMOS pins used. Pull-down resistor (10 kΩ) on output ensures visible logic levels.

Functional Testing

Inputs: two square waves, 2.5 V amplitude, 2.5 V offset. A at 100 Hz, B at 50 Hz. Logic analyzer (AD3) probes A (GPIO1), B (GPIO2), output (GPIO3). Output follows XOR truth table: high when exactly one input is high.

Logic Analysis of CMOS XOR Gate (Figure 4)

Static Testing

Input A fixed at +5 V, B toggled 0–5 V: measured Vout,H=5.01 V, Vout,L=0.042 V. Swapping inputs yields Vout,H=5.02 V, Vout,L=0.041 V. Rounded to 5 V/0 V logic levels.

VH & VL with A fixed at 5V (Figure 5)
VH & VL with B fixed at 5V (Figure 6)

Confirmed logic levels are consistent when swapping fixed input between A and B.

Timing Measurements

To measure propagation delay, a 100 nF capacitor is connected at output. Input B fixed at +5 V, input A toggles 0–5 V. Measured rise/fall times on output: τrise=353 µs, τfall=330 µs. Propagation delays: τPLH=158 µs (Figure 8), τPHL=175 µs (Figure 9). Average τP = (158 + 175)/2 = 166 µs.

Output with 100nF Capacitor (Figure 7)
Zoomed Plot for τPLH (Figure 8)

τPLH Measurement: Input rising to 50%, output rising to 50% = 158 µs.

Zoomed Plot for τPHL (Figure 9)

τPHL Measurement: Input falling to 50%, output falling to 50% = 175 µs.

Bonus: Pass Transistor Implementation

A pass transistor uses NMOS/PMOS as switches to pass signals based on control. XOR via pass-transistor logic uses fewer transistors: 4 for logic, 2 for inverter (total 6 MOSFETs) [2]. When B=0, pass A; when B=1, pass A̅.

XOR with Pass Transistors (Figure 10)
Physical Pass Transistor XOR (Figure 11)

Pass Transistor Testing

Functional Testing

Inputs: same square waves as before (2.5 V amp, 2.5 V offset, A at 100 Hz, B at 50 Hz). Logic analyzer verifies correct XOR output on GPIO3. High when inputs differ, low otherwise.

Logic Analysis of Pass Transistor XOR (Figure 12)
Oscilloscope Output of Pass Transistor XOR (Figure 13)

Static Testing

With one input fixed at +5 V, measured Vout,H=5.01 V, Vout,L=0.06 V (Figure 14). Consistent for either fixed input—rounded to 5 V/0 V.

VH & VL with A Fixed (Figure 14)

Timing Comparison

With 100 nF capacitor on output: τrise=167 µs, τfall=334 µs (Figure 15). Zoomed plots: τPLH=63 µs (Figure 16), τPHL=185 µs (Figure 17). Average τP = (63 + 185)/2 = 124 µs—improved over CD4007B implementation due to parallel NMOS pass transistors reducing Ron.

Pass Transistor Output with Capacitor (Figure 15)
Zoomed Plot for τPLH (Figure 16)
Zoomed Plot for τPHL (Figure 17)

References

  1. A. S. Sedra, K. C. Smith, T. C. Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed. New York, NY: Oxford University Press, 2019. :contentReference[oaicite:0]{index=0}
  2. R. Keim, “Introduction to Pass-Transistor Logic,” Allaboutcircuits.com, Dec. 18, 2018. https://www.allaboutcircuits.com/technical-articles/introduction-to-pass-transistor-logic/ (accessed Apr. 02, 2025).