Manan Dua | CMOS XOR Gate Project

Summary

Logic gates form the basis of digital circuits, and MOSFETs act as voltage-controlled switches. NMOS transistors conduct when their gate is high, while PMOS conduct when their gate is low [1]. CMOS logic uses complementary NMOS and PMOS networks—Pull-Down Network (PDN) of NMOS and Pull-Up Network (PUN) of PMOS—to build efficient, low-power gates. This project implements and tests a CMOS XOR gate using CD4007B arrays.

Design

The XOR function’s Boolean expression is simplified via De Morgan’s theorem. The truth table below shows the expected output logic.

A	B	F (Output)
0	0	0
0	1	1
1	0	1
1	1	0

F = A ⊕ B = A̅B + A B̅
⇒ (A̅B)_̅ · (A B̅)_̅
⇒ (A + B̅) · (A̅ + B)

The PDN consists of A·B̅ in series with A̅·B in parallel. The PUN uses series/parallel reversed logic with PMOS transistors. Inversions of A and B require two additional MOSFETs each. Total component count: 12 MOSFETs.

Ideal Sizing

To minimize delay, the Pull-Up Network (PUN) and Pull-Down Network (PDN) should be symmetric. Propagation delays are calculated as:

τ_PHL = 0.69 × R_N × C_L = 4.14 C_L
τ_PLH = 0.69 × R_P × C_L = 4.14 C_L

Since electron mobility is roughly 2.5× hole mobility, the ideal width ratios should be (W/L)_P : (W/L)_N = 2.5 : 1. For the worst-case scenario (two MOSFETs in series), the size should effectively double to (W/L)_P = 10:1 and (W/L)_N = 4:1. However, the CD4007B has fixed sizes, so ideal sizing is not fully implementable, resulting in a propagation delay approximately 2× τ_ref.

CMOS XOR Gate Implementation

Physical Build

The XOR gate uses two transmission gates (Switch 1 for A·B̅ and Switch 1 mirrored for A̅·B) arranged in PDN and PUN configurations. Inputs A and B feed into inverters (two MOSFETs each) to provide the necessary complementary control signals.

Constructed on a breadboard using one CD4007B IC. All 6 NMOS and 6 PMOS pins on the chip were utilized. A 10 kΩ pull-down resistor was placed on the output to ensure visible logic levels during testing.

Functional Testing

Inputs consisted of two square waves with 2.5 V amplitude and 2.5 V offset. Input A ran at 100 Hz, while Input B ran at 50 Hz. A Logic Analyzer (Analog Discovery 3) probed A (GPIO1), B (GPIO2), and the Output (GPIO3). The output correctly follows the XOR truth table: high only when exactly one input is high.

Static Testing

Input A Fixed High

With Input A fixed at +5 V and B toggled 0–5 V, measured V_out,H = 5.01 V and V_out,L = 0.042 V. This confirms strong logic levels.

Input B Fixed High

Swapping inputs (Input B fixed at +5 V) yielded V_out,H = 5.02 V and V_out,L = 0.041 V. This confirms the circuit is symmetric and logic levels remain consistent regardless of which input is toggled.

Timing Measurements

To measure propagation delay, a 100 nF capacitor was connected at the output to simulate load. Input B was fixed at +5 V, while input A toggled 0–5 V. Measured rise/fall times on output were τ_rise = 353 µs and τ_fall = 330 µs.

Propagation Delay Low-to-High (τ_PLH)

Measured from Input rising to 50% to Output rising to 50% point: 158 µs.

Propagation Delay High-to-Low (τ_PHL)

Measured from Input falling to 50% to Output falling to 50% point: 175 µs.

Average Delay: τ_P = (158 + 175) / 2 = 166 µs.

Bonus: Pass Transistor Logic

A pass transistor uses NMOS/PMOS as switches to pass signals based on control. XOR via pass-transistor logic uses fewer transistors: 4 for logic, 2 for inverter (total 6 MOSFETs) [2]. The logic is simple: When B=0, pass A; when B=1, pass A̅.

Pass Transistor Testing

Functional Verification

Using the same square wave inputs (2.5 V amp, 2.5 V offset), the logic analyzer verifies the correct XOR output on GPIO3. The output is High when inputs differ, and Low otherwise.

Static Performance

With one input fixed at +5 V, we measured V_out,H = 5.01 V and V_out,L = 0.06 V. These results are consistent regardless of which input is fixed, confirming robust logic levels similar to the standard CMOS implementation.

Timing Comparison

With the same 100 nF capacitor load, we measured τ_rise = 167 µs and τ_fall = 334 µs. The calculated average propagation delay was τ_P = 124 µs. This is an improvement over the standard CD4007B implementation (166 µs) due to the reduced R_on from using parallel NMOS pass transistors.

References

A. S. Sedra, K. C. Smith, T. C. Carusone, and V. Gaudet, Microelectronic Circuits, 8th ed. New York, NY: Oxford University Press, 2019.
R. Keim, “Introduction to Pass-Transistor Logic,” Allaboutcircuits.com, Dec. 18, 2018. Link.